The present invention relates to a method and circuit for testing an integrated circuit (IC), and more particularly, to testing the on-resistance of a transistor.
To guarantee that an IC operates properly, the properties of a transistor must be accurately evaluated during a testing stage. In the prior art, the on-resistance of a transistor is measured as an evaluation index.
Japanese Laid-Open Patent Publication No. 2004-226115 describes a method for measuring the resistances of a plurality of output circuits in an IC. In this publication, two of the plurality of output circuits are selectively used during a test, and the on-resistances of the two output transistors forming each output circuit are measured by conducting a four-terminal measurement. One of the two selected output circuits serves as a device under test (DUT), and the other one of the two selected output circuits serves as a reference device that is used with the DUT to measure the on-resistances of the output transistors in the DUT. The output circuits are connected in parallel between a VDD line, which is connected to a VDD terminal, and a GND line, which is connected to a GND line.
During the test, the two transistors of the DUT are both activated, and the two output transistors of the reference device are selectively activated. The voltage and current applied to each output transistor of the DUT is measured using an output terminal of the DUT, an output terminal of the reference device, the VDD terminal, and the GND terminal. The on-resistance is calculated using the voltage and current applied to each output transistor of the DUT. However, the DUT and reference device, that is, the plurality of output circuits are connected to a common power line (VDD line). Thus, in the prior art, the test cannot be conducted when the VDD line is broken. Further, this prior art testing method cannot be directly applied to a multi-power IC, in which a plurality of output circuits are connected to different power lines, such as a multichannel DC/DC converter that generates different power levels. Accordingly, the application of the prior art testing method is restricted since it is dependent on the power supplied to the IC.
Japanese Laid-Open Patent Publication No. 2008-60494 describes a test circuit for measuring the resistance of a motor driver such as an H-bridge. The four-terminal measurement is also conducted in this publication using the test circuit with the H-bridge to measure the on-resistances of four drive transistors that form the H-bridge. The H-bridge is connected to two power terminals, which respectively supply the H-bridge with a high potential voltage and a low potential voltage, and two output terminals, which output in a complementary manner the drive voltage generated by the H-bridge. The test circuit includes four switch elements, each of which is formed by an NMOS transistor. The four switch elements are each connected to a different one of the four terminals of the H-bridge.
During a test, the test circuit selectively activates one of the four switch elements (NMOS transistors) to sequentially measure the voltages of the four terminals of the H bridge through a source-drain path of each switch element. The on-resistance of each drive transistor is calculated from the voltage (measured voltage at two points) and current applied to the drive transistor. In this test circuit, the back gate of each switch element is connected to ground to prevent leakage current from flowing to the switch element during normal operation of a motor driver. In other words, the substrate bias of each switch element is controlled to improve the off property (source-drain disconnection) of each switch element. This prevents the flow of leakage current through each switch element when the switch element is activated. However, to control the gate of each switch element, the test circuit requires another voltage source to supply a voltage that is higher than the voltage (IC power) for controlling the drive transistors of the H-bridge. Therefore, when the voltage value of the IC power becomes high, the structure of the test circuit becomes complicated.